library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipeemreg is
	generic
	(
		DATA_WIDTH	: natural  :=	32;
		REG_WIDTH	: natural  :=	5
	);


	port
	(
		-- Input ports
		-- from pipedereg
		ewreg : in std_logic;
		em2reg : in std_logic;
		ewmem : in std_logic;
		eb : in std_logic_vector(DATA_WIDTH-1 downto 0);
		edesr : in std_logic_vector(REG_WIDTH-1 downto 0);
		-- from pipeexe
		ealu : in std_logic_vector(DATA_WIDTH-1 downto 0);
		-- from outside
		cen : in std_logic;
		clk : in std_logic;
		clrn : in std_logic;
		-- Output ports
		-- to pipeid and pipemwreg
		mwreg : out std_logic;
		mm2reg : out std_logic;
		-- to pipemem
		mwmem : out std_logic;
		malu : out std_logic_vector(DATA_WIDTH-1 downto 0);
		mb : out std_logic_vector(DATA_WIDTH-1 downto 0);
		mdesr : out std_logic_vector(REG_WIDTH-1 downto 0)
	);
end pipeemreg;

architecture rtl_pipeemreg of pipeemreg is
component lpm_dffe32
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;
component lpm_dffe5
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
end component;
component lpm_dffe1
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC 
	);
end component;
signal aclr : std_logic;
begin
	aclr <= not clrn;
	emwreg_r: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => ewreg,
		enable => cen,
		q => mwreg
	);	
	emm2reg_r: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => em2reg,
		enable => cen,
		q => mm2reg
	);
	emmwmem_r: lpm_dffe1 port map(
		aclr => aclr,
		clock => clk,
		data => ewmem,
		enable => cen,
		q => mwmem
	);
	emalu_r: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => ealu,
		enable => cen,
		q => malu
	);
	emb_r: lpm_dffe32 port map(
		aclr => aclr,
		clock => clk,
		data => eb,
		enable => cen,
		q => mb
	);
	emdesr_r: lpm_dffe5 port map(
		aclr => aclr,
		clock => clk,
		data => edesr,
		enable => cen,
		q => mdesr 
	);
end rtl_pipeemreg;
